Method of forming a metal seed layer for subsequent plating

ABSTRACT

A method of forming a metal seed layer, preferably a copper layer, for subsequent electrochemical deposition. The metal seed layer is formed by the oxidation-reduction reaction of a metal salt with a reducing agent present in a layer on the substrate to be plated. Metal interconnects for semiconductor devices may be produced by the method, which has the advantage of forming the metal seed layer by a simple electrochemical plating process that may be combined with the plating of the interconnect itself as a single-bath operation.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of electrochemicaldeposition, and in particular to a method of forming a metal seed layerby electroplating.

BACKGROUND OF THE INVENTION

[0002] The performance characteristics and reliability of integratedcircuits have become increasingly dependent on the structure andattributes of the vias and interconnects which are used to carryelectronic signals between semiconductor devices on integrated circuitsor chips. Advances in the fabrication of integrated circuits haveresulted in increases in the density and number of semiconductor devicescontained on a typical chip. Interconnect structure and formationtechnology has lagged behind these advances, however, and is now a majorlimitation on the signal speed of integrated circuits.

[0003] Current techniques for forming vias and interconnects begin withpreparation of the semiconductor wafer surface by formation of aninterlevel dielectric layer (ILD), typically silicon dioxide. A mask maythen be applied to pattern the deposition of the interconnect materialon the wafer in the desired manner. Another typical process is to platethe interconnect material onto the surface of the wafer to a depthsufficient to fill the vias, followed by planarization to achieve thedesired interconnect pattern.

[0004] Typically the preferred metal for use in the construction ofintegrated circuit interconnects has been aluminum. Aluminum is widelyused because it is inexpensive, relatively easy to etch, and adhereswell to ILDs such as silicon dioxide. Disadvantages of aluminum includesignificant electromigration effects, susceptibility to humidity-inducedcorrosion, and the tendency to “cold creep”. “Cold creep” is a processthat creates cracks or spaces between the interconnect layer and the ILDdue to large variances in the coefficient of thermal expansion betweenthe two materials.

[0005] The disadvantages of aluminum interconnects have become morepronounced as the geometry of integrated circuits continues to shrink.Chip designers have attempted to utilize different materials toconstruct an interconnect system having the chemical and mechanicalproperties which will complement and enhance smaller and faster circuitsystems. The ideal interconnect material is inexpensive, and has lowresistivity, minimal electromigration effects, high corrosionresistance, and a similar coefficient of thermal expansion to the ILDand substrate material. Metals possessing these properties include gold,silver, and copper, and research has generally focused on these threemetals as new via and interconnect materials.

[0006] Copper is the most attractive material for use in integratedcircuits because of its desirable chemical and mechanical properties. Itis an excellent conductor with a resistivity of 1.73 microOhms percentimeter, is inexpensive, and is easily processed. Copper also hasfewer electromigration effects than aluminum and can therefore carry ahigher maximum current density, permitting a faster rate of electrontransfer. The high melting point and ductility of copper produce farless cold creep during the semiconductor fabrication process than manyother metals, including aluminum.

[0007] Although copper has many favorable characteristics, it also hasdisadvantages that may create fabrication problems for chip designers.Copper is soluble in silicon and most common ILDs, and exhibits a highrate of diffusion at temperatures associated with integrated circuitmanufacturing. This diffusion can result in the creation ofintermetallic alloys which can cause malfunctioning of the activesemiconductor devices. In addition, copper exhibits poor adhesion tosilicon dioxide which can result in broken connections and failure ofelectrical contacts.

[0008] Use of an intermediate barrier layer between the ILD and thecopper interconnect permits the successful use of copper in asilicon-based integrated circuit. The barrier layer serves to eliminatethe diffusion that would otherwise occur at the copper-ILD junction, andthus prevents the copper from altering the electrical characteristics ofthe silicon-based semiconductor devices. Such barrier layers are wellknown in the art and may be formed of a variety of transition metals,transition metal alloys or silicides, metal nitrides, and ternaryamorphous alloys. The most common barrier layer materials in use aretitanium, tantalum, and tungsten alloys due to their demonstratedability to effectively reduce copper diffusion.

[0009] Deposition of a metallization layer generally occurs through oneof the following techniques: chemical vapor deposition (CVD); physicalvapor deposition (PVD), also known as sputtering; or electrochemicaldeposition. CVD involves high temperatures which can lead to cold creepeffects and an increased chance of impurity contamination over othermethods, and sputtering has problems yielding sufficient step coverageand density at small line widths. Electrochemical deposition, however,offers a more controlled environment to reduce the chance ofcontamination, and a process that takes place with minor temperaturefluctuations. Electrochemical deposition provides more thoroughcoverage, fewer physical flaws, and reduces separation between thelayers.

[0010] There are several known electrochemical deposition processes usedto form copper interconnects onto barrier layers, each having variousdisadvantages. Direct deposition of copper onto the barrier layertypically results in porous films with poor adhesion and inconsistentdensities. Annealing of the deposited copper at low temperatures may beperformed to improve adhesion, but it increases cold creep effects andfails to provide a consistently dense copper structure. A copper seedlayer may be formed over the barrier layer by CVD or PVD to produce anadhesive surface, and then electrochemical deposition may be carried outon the seed layer. This method involves multiple steps and increasesproduction costs by requiring several different types of machines toform each interconnect layer.

[0011] What is needed, therefore, is a simple and inexpensive method offorming a metal seed layer that requires only a minimum number of stepsfor its production.

SUMMARY OF THE INVENTION

[0012] The present invention provides a method of forming a metal seedlayer, preferably a copper layer, for subsequent electrochemicaldeposition. The metal seed layer is formed by the oxidation-reductionreaction of a metal salt or complex such as copper sulfate in acidsolution, with a reducing agent such as elemental silicon that ispresent in a layer on the substrate to be plated. Preferably thereducing agent is present in a sacrificial layer on the substrate. Themethod is particularly suited to forming metal interconnects forsemiconductor devices, because the metal seed layer and the plating ofthe interconnect itself may be combined into a single-bath operation.

[0013] Additional advantages and features of the present invention willbe apparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross-sectional view of a semiconductor waferundergoing the process of a preferred embodiment of the presentinvention.

[0015]FIG. 2 shows the wafer of FIG. 1 at a processing step subsequentto that shown in FIG. 1.

[0016]FIG. 3 shows the wafer of FIG. 1 at a processing step subsequentto that shown in FIG. 2.

[0017]FIG. 4 shows the wafer of FIG. 1 at a processing step subsequentto that shown in FIG. 3.

[0018]FIG. 5 shows the wafer of FIG. 1 at a processing step subsequentto that shown in FIG. 4.

[0019]FIG. 6 shows the wafer of FIG. 1 at a processing step subsequentto that shown in FIG. 5.

[0020]FIG. 7 is a cross-sectional view of a semiconductor waferundergoing the process of a second preferred embodiment of the presentinvention.

[0021]FIG. 8 shows the wafer of FIG. 7 at a processing step subsequentto that shown in FIG. 7.

[0022]FIG. 9 shows the wafer of FIG. 7 at a processing step subsequentto that shown in FIG. 8.

[0023]FIG. 10 shows the wafer of FIG. 7 at a processing step subsequentto that shown in FIG. 9.

[0024]FIG. 11 shows the wafer of FIG. 7 at a processing step subsequentto that shown in FIG. 10.

[0025]FIG. 12 shows the wafer of FIG. 7 at a processing step subsequentto that shown in FIG. 11.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0026] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical, electrical and chemical changes may be made withoutdeparting from the spirit and scope of the present invention.

[0027] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. When referring to aqueoussolutions described herein, the term “percent” refers to the percentmeasured by weight, e.g., a 10% hydrofluoric acid solution is 10% byweight hydrofluoric acid. The following description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

[0028] Referring now to the drawings, where like elements are designatedby like reference numerals, an embodiment of the present invention formanufacturing an integrated circuit having a metal interconnect isillustrated by FIGS. 1 through 6. The process creates a metal seed layerfor subsequent electrochemical deposition by a oxidation-reduction(“redox”) reaction between a reducing agent present in a sacrificiallayer of material, and a metal salt or complex. For illustrativepurposes the invention is described as a method of plating copper by areaction in which the reducing agent is silicon, but the use of othermetals and reaction mechanisms is to be understood as within the scopeof the invention.

[0029] The process begins subsequent to the formation of a semiconductordevice 20 containing devices 24, which may be transistors, capacitors,word lines, bit lines or the like, and active areas 26 on a siliconsubstrate 22, as shown in FIG. 1. A protective layer 28 of a materialsuch as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG),borosilicate glass (BSG), or silicon dioxide has been formed over thedevice 20 by chemical vapor deposition (CVD) or other suitable means.

[0030] The process of the present invention begins by applying aphotoresist and mask (not shown), and by using photolithographictechniques to define areas to be etched out. Referring to FIG. 2, adirectional etching process such as reactive ion etching (RIE) is usedto etch through the protective layer 28 to form vias 30. The etchantused may be any suitable etchant that selectively etches the material ofthe protective layer 28 and not the active areas 26, the devices 24, orthe material of sidewall or cap insulators on the devices 24.

[0031]FIG. 3 depicts the next step of the process, in which a barrierlayer 32 is formed so that it overlies the protective layer 28 and linesthe inside of the vias 30. Barrier layers are typically used with metalinterconnect material to optimize performance of the interconnects, andto prevent diffusion of the metal interconnect material into thesubstrate. The barrier layer 32 may be formed of any suitable materialsuch as titanium, titanium nitride, tantalum, tantalum nitride, tungstennitride, tungsten-tantalum, tantalum silicon nitride, or other ternarycompounds, and should be of a thickness within the range of 50 to 500Angstroms, and preferably approximately 300 Angstroms thick. Chemicalvapor deposition, physical vapor deposition (PVD), or other suitablemeans may be used to form the barrier layer 32.

[0032] Next, a sacrificial oxide layer 34 is formed over the barrierlayer 32 and lining the inside of the vias 30, as shown in FIG. 4. Thesacrificial oxide layer 34 is a layer of silicon-containing materialsuch as silicon dioxide or silicon monoxide that is formed by means suchas CVD, PVD, oxidation of the wafer in an ozone-containing rinse bath,or the like. Preferably the oxide is a chemical oxide. The sacrificialoxide layer 34 has a thickness within the range of 10 to 200 Angstroms,preferably 10 to 50 Angstroms, and should have a silicon-to-oxygen ratioof greater than 0.5. Depending on the reaction mechanism, a sacrificialoxide layer 34 may not be required, and a reactive barrier layer 32 maybe used if there is a sufficient amount of the reducing agent present inthe barrier layer 32.

[0033]FIG. 5 depicts the next step of the process, in which a metal seedlayer 36 is now formed on the surface of the barrier layer 32 in thevias 30 by a redox plating process. The plating process is carried outby exposing the wafer 20 to a first plating solution by means such asimmersion of the wafer 20 into a plating bath, or by spraying theplating solution onto the wafer 20. The first plating solution is anaqueous solution of an acid such as hydrofluoric acid or sulfulric acid,and a metal salt or complex that is soluble in the acid used. A redoxreaction occurs between the metal ions in the solution, e.g., cupricions (Cu²⁺) and the reducing agent of the sacrificial oxide layer 34,e.g., silicon, leading to reduction of the metal ions and subsequentplating onto the barrier layer 32.

[0034] For example, in a copper plating process, a dilute solution ofhydrofluoric acid (HF) and a salt such as copper sulfate (CuSO₄) is usedto carry out the reaction with a sacrificial oxide layer 34 containingsilicon as a reducing agent. Preferably a solution containingapproximately 1 part hydrofluoric acid per 100 parts water, and about 3grams of copper sulfate per liter is used, and the reaction is allowedto proceed at room temperature for approximately 2 to 2.5 minutes for asacrificial oxide layer 34 that is approximately 50 Angstroms thick. Thetime and temperature may be adjusted as necessary for the thickness ofthe sacrificial oxide layer 34, and to affect the rate of the reaction.The precise reaction that occurs in the copper plating process isunknown, but is currently believed to be:

Si+2Cu²⁺+6 F⁻→SiF₆ ²⁻+2 Cu

[0035] The plating bath in a preferred embodiment is electroless, but anelectrolytic bath may also be used. An electrolytic bath permitsformation of a thicker metal seed layer 36 than an electroless bath,because electrons are continuously replaced by the electric currentapplied and therefore the metal ions, which have an electron affinity,may continuously plate to the barrier layer 32. If desired, the platingprocess may begin as an electroless process, and a voltage may later beapplied to carry out an electrolytic plating process.

[0036] A conductive layer 38 is now formed in the vias 30 to serve as aninterconnect layer, as shown in FIG. 6. The conductive layer 38 is alayer of metal, which may be the same metal as the metal seed layer 36,or a different metal. Preferably the metal seed layer 36 and theconductive layer 38 are layers of the same metal. The conductive layer38 is formed by an electrochemical deposition process such aselectrolytic or electroless plating.

[0037] Preferably the conductive layer is formed by exposing the wafer20 to a second plating solution by means such as immersion of the wafer20 into a plating bath, or by spraying the second plating solution ontothe wafer 20. The second plating solution is typically an aqueoussolution of an acid such as sulfuric acid, a metal salt or complex thatis soluble in the acid used, and several additives. Either electrolessor electrolytic plating, or a combination of the two may be performed asdesired for certain applications. In addition, any number ofsemiconductor wafers may be simultaneously processed by using a largebath, thereby reducing the cost of manufacture.

[0038] If the metal seed layer 36 and the conductive layer 38 are formedfrom the same metal, then the plating process may be carried out in thesame plating bath that was used for formation of the metal seed layer36, and may use the same plating solution. If the metal seed layer 36and the conductive layer 38 are formed from different metals, then thesame tank may be used for both plating processes if the first and secondplating solutions are cycled through the tank. Subsequent to the platingprocess, conventional processing methods, such as planarization of thewafer 20 to isolate the conductive layer 38 into individual contactplugs, may then be used to create a functional circuit from thesemiconductor wafer 20.

[0039] A second embodiment of the present invention is illustrated byFIGS. 7 through 12. Referring to FIG. 7, a semiconductor device 120contains devices 24, active areas 26, and field oxide regions 40 on asilicon substrate 22. A protective layer 28 has been formed over thedevice 120, and conductive plugs 42 extend through the protective layer28 to contact the active areas 26. A protective layer 44 of a materialsuch as BPSG, PSG, BSG, or silicon dioxide has been formed over thedevice 120 by CVD or other suitable means.

[0040] Photolithographic techniques and subsequent etching are then usedto define and form a damascene opening or trench 30, as shown in FIG. 8.Referring now to FIG. 9, a barrier layer 32 is now formed so that itoverlies the protective layer 44 and lines the inside of the trench 30,as explained with reference to FIG. 3 above. Next, a sacrificial oxidelayer 34 is formed over the barrier layer 32 and lining the inside ofthe trench 30, as shown in FIG. 10, and as further described withreference to FIG. 4 above.

[0041]FIG. 11 depicts the next step of the process, in which a metalseed layer 36 is now formed on the surface of the barrier layer 32 inthe trench 30 by a redox plating process, as is described further abovein reference to FIG. 5. Lastly, a conductive layer 38 is formed in thetrench 30 to serve as an interconnect layer, as shown in FIG. 12. Theconductive layer 38 is a layer of metal formed by an electrochemicalprocess, as is described more fully with reference to FIG. 6 above.Subsequent to the plating process, conventional processing methods, suchas planarization of the wafer 120, may then be used to create afunctional circuit from the semiconductor wafer 120.

[0042] As can be seen by the embodiments described herein, the presentinvention encompasses methods of forming a metal seed layer via a redoxreaction with a reducing agent. The reducing agent may be present in asacrificial layer on the substrate to be plated, or may be in anon-sacrificial layer. It should again be noted that although theinvention has been described with specific reference to semiconductorwafers, the invention has broader applicability, and may be used in anyplating application in which a thin self-limiting seed layer is used.

[0043] The above description and drawings are only illustrative ofpreferred embodiments which achieve the objects, features and advantagesof the present invention. It is not intended that the present inventionbe limited to the illustrated embodiments. Any modification of thepresent invention which comes within the spirit and scope of thefollowing claims should be considered part of the present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of plating a metal layer on asubstrate, comprising the steps of: providing a substrate; forming abarrier layer on a top surface of the substrate; forming a metal seedlayer on the barrier layer by reacting the barrier layer with a firstplating solution; and forming a metal layer on the metal seed layer byexposing the substrate to a second plating solution.
 2. The method ofclaim 1, wherein said barrier layer is a layer of material selected fromthe group consisting of titanium, titanium nitride, tantalum, tantalumnitride, tungsten nitride, tungsten-tantalum alloys, tantalum siliconnitride, and other ternary compounds.
 3. The method of claim 1, whereinsaid metal seed layer forming step comprises immersing the substrate inthe first plating solution.
 4. The method of claim 1, wherein said metalseed layer forming step comprises spraying the first plating solution onthe substrate.
 5. The method of claim 1, wherein said metal seed layerforming step is an electroless plating step.
 6. The method of claim 1,wherein said metal seed layer forming step is an electrolytic platingstep.
 7. The method of claim 1, wherein said metal layer forming stepcomprises immersing the substrate in the second plating solution.
 8. Themethod of claim 1, wherein said metal layer forming step comprisesspraying the second plating solution on the substrate.
 9. The method ofclaim 1, wherein said metal layer forming step is an electroless platingstep.
 10. The method of claim 1, wherein said metal layer forming stepis an electrolytic plating step.
 11. The method of claim 1, wherein thefirst plating solution comprises a first aqueous solution of a firstmetal and a first acid, and the second plating solution comprises asecond aqueous solution of a second metal and a second acid.
 12. Themethod of claim 11, wherein the first and second metals are the samemetal.
 13. The method of claim 12, wherein the first and second metalsare copper.
 14. The method of claim 12, wherein the first and secondaqueous solutions are the same.
 15. The method of claim 11, wherein thefirst metal is a metal salt.
 16. The method of claim 11, wherein thefirst metal is a metal complex.
 17. The method of claim 11, wherein thesecond metal is a metal salt.
 18. The method of claim 11, wherein thesecond metal is a metal complex.
 19. The method of claim 11, wherein thefirst and second metals are different metals.
 20. The method of claim11, wherein the first and second metals are metals selected from thegroup consisting of nickel, copper, ruthenium, rhodium, palladium,silver, osmium, iridium, platinum, gold, mercury and polonium.
 21. Themethod of claim 11, wherein at least one of the first and the secondmetals is copper.
 22. The method of claim 1, further comprising a stepof forming a silicon-containing layer on a top surface of the barrierlayer prior to the metal seed layer forming step.
 23. The method ofclaim 22, wherein said silicon-containing layer forming step comprisesoxidizing the substrate in an ozone-containing rinse bath.
 24. Themethod of claim 22, wherein said silicon-containing layer forming stepcomprises deposition of the silicon-containing layer on the substrate.25. The method of claim 22, wherein said silicon-containing layer is alayer of silicon dioxide.
 26. A method of fabricating a conductive layeron a semiconductor substrate, comprising the steps of: providing asemiconductor substrate; forming a silicon layer on a top surface of thesubstrate; forming a metal seed layer from the silicon layer by reactingthe silicon layer with a first plating solution; and forming aconductive layer on the metal seed layer by exposing the substrate to asecond plating solution.
 27. The method of claim 26, wherein saidsilicon layer forming step comprises oxidizing the substrate in anozone-containing rinse bath.
 28. The method of claim 26, wherein saidsilicon layer forming step comprises deposition of the silicon layer onthe substrate.
 29. The method of claim 26, wherein said silicon layerforming step further comprises forming a barrier layer on the topsurface of the substrate and forming the silicon layer on the barrierlayer.
 30. The method of claim 26, wherein said metal seed layer formingstep comprises immersing the substrate in the first plating solution.31. The method of claim 26, wherein said metal seed layer forming stepcomprises spraying the first plating solution on the substrate.
 32. Themethod of claim 26, wherein said metal seed layer forming step is anelectroless plating step.
 33. The method of claim 26, wherein said metalseed layer forming step is an electrolytic plating step.
 34. The methodof claim 26, wherein the first plating solution comprises a firstaqueous solution of a first metal and a first acid, and the secondplating solution comprises a second aqueous solution of a second metaland a second acid.
 35. The method of claim 34, wherein the first and thesecond metals are the same metal.
 36. The method of claim 35, whereinthe first and second metals are copper.
 37. The method of claim 35,wherein the first and the second aqueous solutions are the same.
 38. Themethod of claim 34, wherein the first metal is a metal salt.
 39. Themethod of claim 34, wherein the first metal is a metal complex.
 40. Themethod of claim 34, wherein the second metal is a metal salt.
 41. Themethod of claim 34, wherein the second metal is a metal complex.
 42. Themethod of claim 34, wherein the first and second metals are differentmetals.
 43. The method of claim 34, wherein the first and second metalsare metals selected from the group consisting of nickel, copper,ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold,mercury and polonium.
 44. The method of claim 34, wherein at least oneof the first and the second metals is copper.
 45. The method of claim26, wherein said conductive layer forming step is an electroless platingstep.
 46. The method of claim 26, wherein said conductive layer formingstep is an electrolytic plating step.
 47. A method of forming a metalinterconnect for a semiconductor circuit, comprising the steps of:providing a semiconductor substrate having electronic devices formedthereon; forming a barrier layer on a top surface of the substrate andthe devices; forming a metal seed layer on the barrier layer by reactingthe barrier layer with a first plating solution; and forming a metalinterconnect layer on the metal seed layer by exposing the substrate toa second plating solution.
 48. The method of claim 47, wherein saidbarrier layer forming step comprises chemical vapor deposition.
 49. Themethod of claim 47, wherein said barrier layer forming step comprisesphysical vapor deposition.
 50. The method of claim 47, wherein thebarrier layer is a layer of material selected from the group consistingof titanium, titanium nitride, tantalum, tantalum nitride, tungstennitride, tungsten-tantalum alloys, tantalum silicon nitride, and otherternary compounds.
 51. The method of claim 47, wherein said metal seedlayer forming step comprises immersing the substrate in the firstplating solution.
 52. The method of claim 47, wherein said metal seedlayer forming step comprises spraying the first plating solution on thesubstrate.
 53. The method of claim 47, wherein said metal seed layerforming step is an electroless plating step.
 54. The method of claim 47,wherein said metal seed layer forming step is an electrolytic platingstep.
 55. The method of claim 47, wherein said metal interconnect layerforming step comprises immersing the substrate in the second platingsolution.
 56. The method of claim 47, wherein said metal interconnectlayer forming step comprises spraying the second plating solution on thesubstrate.
 57. The method of claim 47, wherein said metal interconnectlayer forming step is an electroless plating step.
 58. The method ofclaim 47, wherein said metal interconnect layer forming step is anelectrolytic plating step.
 59. The method of claim 47, wherein the firstplating solution comprises a first aqueous solution of a first metal anda first acid, and the second plating solution comprises a second aqueoussolution of a second metal and a second acid.
 60. The method of claim59, wherein the first and second metals are the same metal.
 61. Themethod of claim 60, wherein the first and second metals are copper. 62.The method of claim 60, wherein the first and second aqueous solutionsare the same.
 63. The method of claim 60, wherein the first metal is ametal salt.
 64. The method of claim 60, wherein the first metal is ametal complex.
 65. The method of claim 60, wherein the second metal is ametal salt.
 66. The method of claim 60, wherein the second metal is ametal complex.
 67. The method of claim 59, wherein the first and secondmetals are different metals.
 68. The method of claim 59, wherein thefirst and second metals are metals selected from the group consisting ofnickel, copper, ruthenium, rhodium, palladium, silver, osmium, iridium,platinum, gold, mercury and polonium.
 69. The method of claim 59,wherein at least one of the first and the second metals is copper. 70.The method of claim 47, further comprising a step of forming a siliconlayer on a top surface of the barrier layer prior to the metal seedlayer forming step.
 71. The method of claim 70, wherein said siliconlayer forming step comprises oxidizing the substrate in anozone-containing rinse bath.
 72. The method of claim 70, wherein saidsilicon layer forming step comprises deposition of the silicon layer onthe substrate.
 73. The method of claim 70, wherein the silicon layer isa layer of silicon dioxide.
 74. The method of claim 70, wherein thesilicon layer is a layer of silicon monoxide.
 75. A method of forming ametal interconnect for a semiconductor circuit, comprising the steps of:providing a semiconductor substrate having electronic devices formedthereon; forming a silicon oxide layer on a top surface of the substrateand the devices; forming a metal seed layer from the silicon oxide layerby reacting the silicon oxide layer with a first plating solutioncontaining a first metal; and forming a metal interconnect layer on themetal seed layer by exposing the substrate to a second plating solutioncontaining a second metal.
 76. The method of claim 75, wherein saidsilicon oxide layer forming step comprises oxidizing the substrate in anozone-containing rinse bath.
 77. The method of claim 75, wherein saidsilicon oxide layer forming step comprises deposition of the siliconoxide layer on the substrate.
 78. The method of claim 75, wherein thesilicon oxide layer has a thickness within the range of approximately 10to 200 Angstroms.
 79. The method of claim 75, wherein the silicon oxidelayer has a thickness within the range of approximately 10 to 50Angstroms.
 80. The method of claim 75, wherein said silicon oxide layeris a layer of silicon dioxide.
 81. The method of claim 75, wherein saidsilicon oxide layer forming step further comprises forming a barrierlayer on the top surface of the substrate and forming the silicon oxidelayer on the barrier layer.
 82. The method of claim 81, wherein thebarrier layer is a layer of material selected from the group consistingof titanium, titanium nitride, tantalum, tantalum nitride, tungstennitride, tungsten-tantalum alloys, tantalum silicon nitride, and otherternary compounds.
 83. The method of claim 75, wherein said metal seedlayer forming step comprises immersing the substrate in the firstplating solution.
 84. The method of claim 75, wherein said metal seedlayer forming step comprises spraying the first plating solution on thesubstrate.
 85. The method of claim 75, wherein said metal seed layerforming step is an electroless plating step.
 86. The method of claim 75,wherein said metal seed layer forming step is an electrolytic platingstep.
 87. The method of claim 75, wherein the first metal is copper. 88.The method of claim 87, wherein the first plating solution is an aqueoussolution of copper sulfate and hydrofluoric acid.
 89. The method ofclaim 75, wherein said metal interconnect layer forming step comprisesimmersing the substrate in the second plating solution.
 90. The methodof claim 75, wherein said metal interconnect layer forming stepcomprises spraying the second plating solution on the substrate.
 91. Themethod of claim 75, wherein said metal interconnect layer forming stepis an electroless plating step.
 92. The method of claim 75, wherein saidmetal interconnect layer forming step is an electrolytic plating step.93. The method of claim 75, wherein the second metal is copper.
 94. Themethod of claim 93, wherein the second plating solution is an aqueoussolution of copper sulfate and hydrofluoric acid.
 95. The method ofclaim 75, wherein the first and second metals are selected from thegroup consisting of nickel, copper, ruthenium, rhodium, palladium,silver, osmium, iridium, platinum, gold, mercury and polonium.
 96. Amethod of plating copper onto a substrate, comprising the steps of:providing a substrate; forming a barrier layer on a top surface of thesubstrate; forming a silicon oxide layer on the barrier layer; forming acopper seed layer from the silicon oxide layer by reacting the siliconoxide layer with a plating solution containing copper and an acid; andforming a copper layer on the copper seed layer by exposing thesubstrate to the plating solution for a time sufficient to produce adesired thickness of the copper layer.
 97. The method of claim 96,wherein the silicon oxide layer is a layer of silicon dioxide.
 98. Themethod of claim 96, wherein the silicon oxide layer has a thicknesswithin the range of approximately 10 to 200 Angstroms.
 99. The method ofclaim 96, wherein the silicon oxide layer has a thickness within therange of approximately 10 to 50 Angstroms.
 100. The method of claim 96,wherein the barrier layer is a layer of material selected from the groupconsisting of titanium, titanium nitride, tantalum, tantalum nitride,tungsten nitride, tungsten-tantalum alloys, tantalum silicon nitride,and other ternary compounds.
 101. The method of claim 96, wherein thebarrier layer has a thickness within the range of 50 to 500 Angstroms.102. The method of claim 96, wherein the barrier layer has a thicknessof approximately 300 Angstroms.
 103. The method of claim 96, wherein theplating solution contains a copper salt.
 104. The method of claim 103,wherein the acid is sulfuric acid.
 105. The method of claim 103, whereinthe plating solution comprises an aqueous solution of copper sulfate andhydrofluoric acid.
 106. The method of claim 105, wherein the platingsolution comprises approximately 3 grams of copper sulfate per liter ofplating solution.
 107. The method of claim 96, wherein the platingsolution contains a copper complex.
 108. The method of claim 96, whereinthe plating solution comprises approximately 1 part hydrofluoric acidper 100 parts water.
 109. The method of claim 96, wherein said copperseed layer forming step is an electroless plating step.
 110. The methodof claim 96, wherein said copper layer forming step is an electrolyticplating step.
 111. A method of forming a copper interconnect for asemiconductor circuit, comprising the steps of: providing asemiconductor substrate having devices formed thereon; forming a barrierlayer on a top surface of the substrate and the devices, wherein thebarrier layer has a thickness of approximately 50 to 500 Angstroms;forming a silicon dioxide layer on the barrier layer, wherein thesilicon dioxide layer has a thickness of approximately 10 to 200Angstroms; forming a copper seed layer from the silicon dioxide layer byreacting the silicon dioxide layer with a plating solution containingcopper sulfate and dilute hydrofluoric acid; and forming a copper layeron the copper seed layer by exposing the substrate to the platingsolution for a time sufficient to produce a desired thickness of thecopper layer.